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2025년 4월 23일(수) 09:00 – 16:40 |
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잠실 소피텔 앰배서더 서울, 그랜드 볼룸 방돔(4F) |
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행사문의 02-501-3614 justin@ispring.co.kr |
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고객이 최대한 빠르고 쉽게 칩 설계부터 테이프 아웃까지 진행할 수
있도록 한다
이것은 Calibre의 가장 중요한 목표로, Calibre의 가장 중요한 가치는
우리가 제공하는 소프트웨어와 반도체 에코시스템 내에서 일하는 방식에
있습니다.
Calibre Design 솔루션은 IC 검증 분야의 업계 리더로서, 설계 생성부터
제조까지 모든 승인 요구 사항을 해결하고 설계 속도를 높여주는 완벽한
IC 검증 및 DFM 최적화 EDA 플랫폼을 제공합니다. Calibre는 EM/IR,
신뢰성, 3D 분석, PERC AFS, 클라우드 등과 관련된 고객의 요구를
해결하고 있으며, 상황 인식 ESD 시뮬레이션, InsightEDA, Calibre
3DThermal, 3D steres를 위한 Calibre 프로젝트 글래시어, 설계 디버그를
위한 프로젝트 볼더, 전체 3DIC 솔루션을 위한 프로젝트 PERC-recon,
프로젝트 델타 등의 로드맵을 포함합니다. 또한 가능한 한 빨리
테이프아웃을 완료하는 데 도움이 되는 더 많은 AI 알고리즘을
통합했습니다.
EDA 업계에서 가장 정확하고, 가장 신뢰할 수 있으며, 최고의 성능을
자랑하는 IC 사인오프 및 검증 DFM 최적화를 제공하는 Siemens EDA의
Calibre 솔루션의 현재와 미래를 만나보세요.
Agenda
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Time
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Session |
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| 09:00 – 10:00 |
등록 / 웰컴 커피 |
| 10:00 – 10:20 |
Opening Speech |
| 10:20 – 11:00 |
Innovator3D IC – Siemens EDA’s Comprehensive Multiphysics Cockpit for 3D IC design Siemens EDA 김경록 This session introduces how to implement the emerging 3D IC heterogeneous integration technologies through end-to-end Siemens EDA solution and methodologies. ‘Innvator3D IC’ is a cockpit platform that addresses comprehensive multi-physics analysis, and this workflow can be used for early pre-implementation predictive verification and analysis as well as sign-off, all driven from a digital twin model of the entire product assembly. Through this session, you will see how ‘Innvator3D IC’ provides best-in-class differentiators to users so they can resolve heterogenous packaging challenges such as total design cycle time, minimizing design re-spins, and system level assembly verification based on practical use cases. |
| 11:00 – 11:40 |
Enhancing Design Efficiency and Quality with Calibre DesignEnhancer Siemens EDA 김세홍 Calibre DesignEnhancer is a powerful tool that enhances design quality and reduces TAT as part of the 'Shift Left' initiative. It enables designers to strengthen vias and power grids, effectively addressing IR drop issues. Additionally, designers can easily insert DECAP, ECO, and filler cells, all while maintaining consistent 'Calibre Clean' results. The tool supports industry-standard formats such as GDS, OASIS, and LEF/DEF for input, and generates GDS, OASIS, and incremental DEF outputs, ensuring a user-friendly experience. |
| 11:40 – 13:00 |
점심식사 |
| 13:00 – 13:40 |
Aprisa, Digital Implementation with Calibre solutions(DRC/PM/MFill/etc.) Siemens EDA 김태경, 정수윤 Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. This session will introduce how to brings Calibre solutions into the Aprisa environment, enabling digital designers to get signoff-quality feedback on early-stage designs, accelerating the design closure and shaving weeks off their tape-out schedule. |
| 13:40 – 14:20 |
What does shift left with Calibre mean for IC designers? Siemens EDA 한정무 Driven by the world’s seemingly insatiable demand for electronics that constantly do more faster, IC design companies are continuously seeking ways to profitably deliver products with more functionality, reliability and performance while reducing time-to-market. To accomplish this, a well-planned shift left strategy can free up critical time and resources in delivery schedules while maintaining or improving product quality. In this session, you will discover the tools, techniques and functionality that are available and how implementing a shift left verification strategy impacts IC designers and P&R engineers. |
| 14:20 – 14:40 |
커피 브레이크 |
| 14:40 – 15:20 |
Advanced Calibre DFM Solutions for design analysis and validation Siemens EDA 김완호 DFM solutions developed by Calibre Fab solution team for design analysis and validation are introduced in this session. Calibre LFD (litho friendly design) servers as the most immediate close loop mechanism bringing confirmed Fab hotspot information to designer via PDK and latest ML-LFD introduces astonishing performance advantage and being OPC vendor agnostic. Calibre SONR (state of nature reduction), a SVRF-based ML Platform, enables Customizable & scalable integrated design and fab interaction analytics such as CAG generation, layout clustering and comparison. Designers and process &QA engineers suffer from insufficient test cases during development & QA. Calibre LSG (layout schema generator) helps producing realistic random layout to improve design space coverage and validate their applications. |
| 15:20 – 16:00 |
Customer co-presentation Full Path P2PCD and 2D Fracturing with real world application Siemens EDA 변선수, FADU 박휘종 책임연구원 This presentation introduces new enhancements to CalibreKR CheckStore’s ‘Output Driver P2PCD’, featuring ‘Full-Path P2PCD’ and ‘2D Fracturing’. These features improve accuracy, efficiency, and usability in design verification. We will explore their functionalities, benefits, and real-world application by FADU. Attendees will gain insights into how these advancements enhance workflow and productivity. |
| 16:00 – 16:30 |
질의응답 |
| 16:30 – 16:40 |
폐회사 / 경품추첨 |
Information
02-501-3614
Justin@ispring.co.kr